==============================================================
Guild: wafer.space Community
Channel: Information / questions / Metal Fill
After: 11/30/2025 23:59
Before: 01/01/2026 00:00
==============================================================

[12/01/2025 05:30] buck_042
@Leo Moser (mole99) Hi mole99, may I ask a further question?  Can I ask why only this much metal is filled here? It seems the density requirement is still not met. Is this normal? Thank you very much!

{Attachments}
2025-12_media/image-D9BC8.png
2025-12_media/image-5A019.png
2025-12_media/image-48708.png


[12/01/2025 06:06] mole99
The filler generation script was made to fill an entire chip, so it adheres to rules such as leaving a 26um spacing from the edges to meet the 10um distance to the sealring etc.
I assume this is what leads to what we see here.


[12/01/2025 06:29] buck_042
I see, thanks! I think this works. We do this because we will integrate this module to our analog module.

{Attachments}
2025-12_media/image-E41E3.png
2025-12_media/image-D29BE.png

{Reactions}
👍

[12/01/2025 06:49] buck_042
Oh I see, actually we don't need fill the digital module at this stage, like we can fill all during the top level?


[12/01/2025 07:34] mole99
Yes, that is the usual approach. The fill for the entire chip is added at the end.

If you do an analog top-level integration you can add the fill manually:

```
klayout -b -zz -r ${PDK_ROOT}/${PDK}/libs.tech/klayout/tech/drc/filler_generation/fill_all.rb -rd input=chip_top.gds -rd output=chip_top_filled.gds
```


[12/01/2025 15:13] buck_042
Hi Leo, thank you! If we want to do top-level integration, may I ask how to obtain a clean pad ring without any logic cells? My current idea is to follow the template, remove everything in the Verilog except VDD/VSS and the pad instances, and remove the metal fill step in the flow, and then rerun the synthesis and PnR flow. Is this the correct approach?


[12/01/2025 15:17] mole99
There is an easier approach :)
You customize the flow to only generate the padring + sealring and then streamout the GDS. I already did this for the MOSbius group: https://github.com/wafer-space/gf180mcu-project-template/pull/29


[12/01/2025 15:26] buck_042
Thank you, this is very helpful! So with this, can we still configure our IO plan? Like, by changing the pad instances in Verilog and the IO placement inside the config.yaml.


[12/01/2025 15:29] mole99
Yes, it still uses the LibreLane configuration. It simply rearranges the flow slightly.


[12/01/2025 15:30] mole99
There were XOR errors between magic and KLayout (?) but I haven't had the time to look into it. Maybe you could see what the difference between the two layouts is.


[12/01/2025 15:34] buck_042
Thank you, this is helpful!

{Reactions}
👍

[12/01/2025 15:36] buck_042
I will try to do that. But to be honest, we are trying to catch up with the DDL now. 😂  See what we can help. Really thank you, Leo!


[12/01/2025 15:37] mole99
Yes, just make sure to use the correct layout then if there is a difference between magic and KLayout 😁
No worries! Looking forward to your design.


[12/01/2025 22:17] xintingjiang_36756
I also encountered this when generating the empty pad frame today. Now I am looking into the differences between the two layouts


[12/01/2025 22:43] xintingjiang_36756
In my case, klayout gds is correct because I found that the only mismatch is that the magic gds has these extract tieh and tiel cells at the origin and I don't know why

{Attachments}
2025-12_media/6ED7F713-7F6F-4110-92A3-15E65CBCDAF2-4EA44.png


[12/02/2025 07:34] mole99
Right, that's the difference! It seems that magic exports the instances even if they were not placed. There are some constants that are used in `chip_top`, but we stream out the padring before any of those stdcells can be placed and routed. 
So the KLayout version is the correct one to use.


[12/03/2025 15:26] buck_042
Hi Leo, may I ask a question? We are doing analog top-level integration now, so after we connect our design to the pad ring, is this the last step before DRC and LVS? Or any other step we should run? Thank you!


[12/03/2025 15:29] mole99
Hi Buck, sure thing. You should also generate the fill before doing DRC and LVS, but other than that, that should be it.

{Reactions}
👍

[12/03/2025 15:30] buck_042
Thanks!


[12/09/2025 02:19] buck_042
@Leo Moser (mole99) Hi Leo, sorry to bother you again, after we do the top level analog style integration and do the fill step, is there any script or command that we can use to tun the drc check in librelane environment? Before we used chipathon environment. Thanks!

{Attachments}
2025-12_media/image-8B689.png


[12/09/2025 06:23] 246tnt
If you run the pre-check, it will run DRC.


[12/09/2025 07:24] mole99
As Sylvain said, you can run the precheck.
This can be done either through the online platform (https://platform.wafer.space/) or locally (https://github.com/wafer-space/gf180mcu-precheck).
Alternatively, you can run the DRC deck directly: https://github.com/wafer-space/gf180mcu/blob/main/gf180mcuD/libs.tech/klayout/tech/drc/gf180mcu.drc


[12/09/2025 19:03] buck_042
Thanks!


==============================================================
Exported 23 message(s)
==============================================================