wafer.space Community - Running LVS for padframe

Hi everyone, We are trying to run LVS checks for the PADs in gf180mcu using netgen. Not sure if others are using the same for it or maybe can suggest another tool to do it. However, while we achieved passing successfully for other circuits, for the pads (provided by GF) seems that it is no passing. We are trying with a simple test case of 4 pads, vdd, vss, asig5v and fills. What we found is that in all the pads there is an extra net which is not present (not matched) in schematic. Digging into the issue we identified that the extracted spice netlist from layout is creating diodes with just one pin exposed while the another is connected to substrate. Not sure if netgen understands VSUBS as a global net, but the anode (substrate) is being considered as floating net during the comparison. The layout also seems to have just one pin exposed, so the extraction might be OK but might require something in netgen configuration to make it work. Have anyone faced this issue?, or can provide a guidance to configure the LVS tool properly? Thank you! cc: @peterkinget

@LuighiV I think you may have run into the issue that magic does not handle devices that are formed by layers on different hierarchies. I have LVS pass on the gf I/O cells by flattening before extracting via gds flatglobing the following.

*Bondpad*
*CLAMP_COR*
*FILL*
*METAL_RAIL*
*NMOS_*
*POWER_RAIL_COR*
*_BASE*
*comp018green*  
*diode_nd2ps_06v0_*[A-Z]*
*diode_pd2nw_06v0_*[A-Z]*
*mim_*_*[A-Z]*  
*moscap_*
*nmos_*_*[A-Z]* 
*nmos_4T_metal_stack*
*nmos_clamp_*   
*pmos_6p0_esd_* 
*power_via*     
*ppolyf_u_*[A-Z]*
*top_route*     
*_CDNS_*

(edited to include *_CDNS_*) (edited)

2

Hi @bailey that's great you have already managed to make it work, let me try the same here, thanks for the advice

2

Hi @bailey I have used the configuration you have shared, and now the difference is in the 3rd terminal of poly resistors. In layout is connected to VSS while in the netlist is connected to VDD. Do you know how to fix this? I'm using the spice model shared in the Chipathon repository

@LuighiV The actual layout looks like it's over nwell, so DVDD should be the proper connection. Can you share the extracted netlist?

sure, the extrated one is attached here

sample_pads_layout.spice

188.17 KB

@LuighiV magic extracts devices at the level the occur in the hierarchy. It has problems, for example, if you add a nwell at a parent hierarchy. For the I/O cells to extract correctly, I had to gds flatglob all the subcells. The final extracted netlist should only include subckts for the top level io cells.

bailey

@LuighiV magic extracts devices at the level the occur in the hierarchy. It has problems, for example, if you add a nwell at a parent hierarchy. For the I/O cells to extract correctly, I had to gds flatglob all the subcells. The final extracted netlist should only include subckts for the top level io cells.

Hi @bailey thanks for the heads up, I was using the set of instruction you shared before, I guessed that way will flatten he internal hierarchies, do you why it keeps extracting the subhierarchies?

run_lvs.sh

2.81 KB

@LuighiV Looks like I missed one. Try adding gds flatglob *_CDNS_*

oh, got it, let me try again, thanks

1

Hi @bailey I re run again but seems it has the same issue, and it keeps extracting the internal hierarchies

sample_pads_comp.out

29.38 KB

run_lvs.sh

2.83 KB

sample_pads_layout.spice

188.17 KB