wafer.space Community - Setup Violations in tt corners when using macros

Hi everyone, we are building our toplevel module out of several designs by using macros. We only have one clock input which is routed to all macros, but they do not run at the same clock frequency. Of course, the timing analysis finds Setup Violations in some macros if the toplevel period is smaller than the period of the macro. But how should we go about this? STA finds Setup Violations in the TT corners and then errors out. Is this fine if we know that the macro will never be used at this frequency or do we at least have to fix all errors?

Jonathan

Hi everyone, we are building our toplevel module out of several designs by using macros. We only have one clock input which is routed to all macros, but they do not run at the same clock frequency. Of course, the timing analysis finds Setup Violations in some macros if the toplevel period is smaller than the period of the macro. But how should we go about this? STA finds Setup Violations in the TT corners and then errors out. Is this fine if we know that the macro will never be used at this frequency or do we at least have to fix all errors?

I'm pretty sure the precheck does not do any timing analysis. (edited)

22:23

You might be able to do something trickly like put in a clock buffer per macro and use sdc to set the maximum frequency on the clock buffer output....

22:24

The Tiny Tapeout people like @tnt and @urish might have some other ideas?

The pre-check doesn't do any STA indeed so if you're confident that the violations are false positives you can ignore it. But you could also write a custom SDC that just sets up the constraints correctly for each submodule.

Tim 'mithro' Ansell

I'm pretty sure the precheck does not do any timing analysis. (edited)

The precheck runs without problems. I was just concerned about the "make librelane" flow, since this one ends with an error due to Setup Violations in the tt corner in this case. Does an error prevent some part of the flow from being run? From the log files it seems that every step was executed

No, STA errors won't prevent anything from running, they're just informations.

08:08

If you get something in the final subdir, then all the steps ran.

Jonathan

The precheck runs without problems. I was just concerned about the "make librelane" flow, since this one ends with an error due to Setup Violations in the tt corner in this case. Does an error prevent some part of the flow from being run? From the log files it seems that every step was executed

You can add "Checker.SetupViolations: null" to the substituting_steps section of config.yaml to stop the LibreLane from failing a flow on timing violations. (edited)

Okay, thanks very much. I will try that

Oh, looks like my info is outdated, I wasn't even aware that flow failed on STA violation now, sorry about that.

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