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Guild: wafer.space Community
Channel: Information / questions / SRAM rules
After: 10/31/2025 23:59
Before: 12/01/2025 00:00
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[11/28/2025 17:55] 246tnt
Are the SRAM rules only valid for foundry provided cell ? What if I want to design my own memory array or dual port cell or stuff like that, can I use them ?


[11/28/2025 19:12] mole99
Yes, I think that should be possible.
Afaik it's not the cells that are detected, but rather the SRAM marker layer.
However, as you probably know, there's no guarantee your cells will work after production, since the SRAM cells in the PDK were probably carefully designed to violate the normal core rules.


[11/28/2025 19:14] mole99
In fact, @Tim Edwards  already shrinked the 5V SRAM cells.


[11/28/2025 19:15] 246tnt
I know he did but they are still 6T cells, I'm thinking about doing the same register file that I did on sky130, or a dual port cell, or rom or other things like that.

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[11/28/2025 19:17] mole99
Yes, as long as you place the SRAM marker layer you can use the SRAM 3.3V/5V rules, as I understand it.

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[11/28/2025 22:37] mithro_
When using the SRAM cells DRC rules there are normally a bunch of requirements around the layout of the cells that are not specified in DRC decks and such.


[11/28/2025 22:38] mithro_
My understanding is that they can violate the rules due to the tuning to make the regular patterns print better.


[11/29/2025 07:38] mole99
These rules are documented here:
- https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_11_1.html
- https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_11_2.html

So it should be possible to submit your own custom cells based on these rules, but there is no guarantee that they will work as expected.


[11/29/2025 16:52] rtimothyedwards_19428
Since I created the 3.3V SRAM core cell myself, we'll put that theory to the test.

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[11/30/2025 01:49] mithro_
Yeap! I'm interested to see how things go, I don't quite have the same pull with GF now I'm not Google.

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