wafer.space Community - What mimcaps can we use on gf180mcu?

Insert obligatory "Sorry if this was really obvious..." here. When placing mimcaps in layout, we have the option for mimcap option MIM-A or MIM-B, and also the option to choose which layers we place between. This post seems to suggest that we should use MIM-B between M4-M5 (on top of M4).

Is MIM-B with M4-M5 the only MIM configuration we're allowed to use? What others can we use, if any?

The docs page referenced in the above message suggests there are two possibilities for the SiN thickness, which lead to different capacitances.

What is the SiN thickness used in waferspace gf180mcu?

Thanks.

Yes, MIM-B is what you can use.

5:28 a.m.

1.5 fF / um^2 is the config used

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5:31 a.m.

This is for a full wafer.space slot right ? Not for tinytapeout ?

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Stackup can be found here: https://gf180mcu-pdk.readthedocs.io/en/latest/analog/layout/inter_specs/inter_specs_3_43.html (Sorry, already linked above). (edited)

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tnt

This is for a full wafer.space slot right ? Not for tinytapeout ?

it's half height on wafer.space. it's not tinytapeout tbqh, i have a hard time finding the specific options chosen by wafer.space for gf180mcu, is there a more organized doc anywhere that lists all details of the specific configuration? (edited)

Like what ?

9:48 p.m.

The PDK itself gf180mcuD variant will show most details when looking in the tech files.

does that mention (for examples) which mimcap config is used and that the ppolyf_u_high_Rs is 1k? i could just have not read them properly

For now, the best way to get that information is to read the magic techfile for gf180mcuD.

**Note that there are multiple mutually exclusive process options for the high sheet rho resistor and MiM capacitor. This tech file assumes the options 1kOhm/sq for the resistor and 2fF/um for the MiM capacitor.

However, this is a surprise to me, since I would have expected 1.5fF/um2 or 1.0fF/um2. The device is called cap_mim_2f0_m4m5_noshield, which would also suggest 2fF, but I don't even see that option the in the stackup? The only place I can find 2.0fF in the documentation is on this page, which shows strange model names for the MIM caps: https://gf180mcu-pdk.readthedocs.io/en/latest/analog/model_parameters/LV/LV_1_4_6.html It seems to incorrectly use the model names from the MOSCAP models: https://gf180mcu-pdk.readthedocs.io/en/latest/analog/model_parameters/LV/LV_1_4_5.html @Tim Edwards do you have any idea what's going on here? (edited)

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@Leo Moser (mole99) Interestingly I was seeing that in the E-Test results. The test result is named "MIM15_A" suggesting 1.5fF/um^2 but then the spec is 1.7 fF/um^2 minumum and 2.3 fF/um^2 maximum and we hit 1.92 fF/um^2 on run 1.

tnt

@Leo Moser (mole99) Interestingly I was seeing that in the E-Test results. The test result is named "MIM15_A" suggesting 1.5fF/um^2 but then the spec is 1.7 fF/um^2 minumum and 2.3 fF/um^2 maximum and we hit 1.92 fF/um^2 on run 1.

That is indeed strange. I would also have expected "B" in the name, not "A".

@Leo Moser (mole99) Looking at https://mithro-gf180mcu-pdk.readthedocs.io/en/latest/analog/spice/elec_specs/elec_specs_6_4.html

7:36 a.m.

I think there are two orthogonal options. Where the cap is in the metal and what thickness of dielecric.

7:38 a.m.

So the "A" in tha test might refer to option a on that page which is indeed 1.5 f/F. Now why doesn't that match the option we think we have and the min/max value ... I'm starting to think the labels have been cut or only reflect the first option or somethign which would also explain why the label mention 9K top metal while we should have 11 K one.

The choice of MiM capacitance and the choice of poly high sheet rho resistance is entirely by process option, and there is no indication in the way of layer ID markers to indicate which option is which, or to prevent the end user from designing to the wrong option and then submitting the design. It is entirely up to everyone involved to be on the same page, which is honestly a bit scary. This is why I have in the magic tech file the comment about "this tech file assumes the options. . .". There is literally no other way to convey that information. The only other place it's decided is when Wafer Space submits the form to GF. I expect that the E-test structures are just named the same thing without regard to the actual options chosen, which probably works better with the automation doing the testing. The actual options chosen are a bit arbitrary; I made those choices in deciding what options Efabless would use for the Google/GF shuttle run. My intent was to try to get the same MiM cap density as the double MiM structure on sky130. In retrospect, the sky130 res_xhigh (2kohms/square) is used much more often than the res_high and would probably have been a better choice. (edited)

Leo Moser (mole99)

For now, the best way to get that information is to read the magic techfile for gf180mcuD.

**Note that there are multiple mutually exclusive process options for the high sheet rho resistor and MiM capacitor. This tech file assumes the options 1kOhm/sq for the resistor and 2fF/um for the MiM capacitor.

However, this is a surprise to me, since I would have expected 1.5fF/um2 or 1.0fF/um2. The device is called cap_mim_2f0_m4m5_noshield, which would also suggest 2fF, but I don't even see that option the in the stackup? The only place I can find 2.0fF in the documentation is on this page, which shows strange model names for the MIM caps: https://gf180mcu-pdk.readthedocs.io/en/latest/analog/model_parameters/LV/LV_1_4_6.html It seems to incorrectly use the model names from the MOSCAP models: https://gf180mcu-pdk.readthedocs.io/en/latest/analog/model_parameters/LV/LV_1_4_5.html @Tim Edwards do you have any idea what's going on here? (edited)

Thanks, I totally missed that scrolling through/grepping for things I thought would match. Based on the defined subckts from gf180mcuD/libs.tech/ngspice/sm141064_mim.ngspice (the path as in IIC-OSIC-TOOLS), it seems the documentation is incorrect here. ('documentation' referring to the stackup page: https://gf180mcu-pdk.readthedocs.io/en/latest/analog/layout/inter_specs/inter_specs_3_43.html) So, I assume in layout (KLayout) I can use cap_mim with MIM-B and M4-M5 options selected, but expect the final capacitance to be ~2.0fF/um^2 for simulation purposes. Is this correct?

Tim Edwards

The choice of MiM capacitance and the choice of poly high sheet rho resistance is entirely by process option, and there is no indication in the way of layer ID markers to indicate which option is which, or to prevent the end user from designing to the wrong option and then submitting the design. It is entirely up to everyone involved to be on the same page, which is honestly a bit scary. This is why I have in the magic tech file the comment about "this tech file assumes the options. . .". There is literally no other way to convey that information. The only other place it's decided is when Wafer Space submits the form to GF. I expect that the E-test structures are just named the same thing without regard to the actual options chosen, which probably works better with the automation doing the testing. The actual options chosen are a bit arbitrary; I made those choices in deciding what options Efabless would use for the Google/GF shuttle run. My intent was to try to get the same MiM cap density as the double MiM structure on sky130. In retrospect, the sky130 res_xhigh (2kohms/square) is used much more often than the res_high and would probably have been a better choice. (edited)

Once I have PCells for the R-4R (or possibly closer to R-3R; it will depend on yield target and demands on output impedance/how-buffered the output is; e.g. current-mode feeds a virtual ground instead of directly the load) DAC and some replica-bias based MCML logic gates, I'd happily provide comparisons on performance and area impact of instead instantiating them with different sheet resistor option; ofc. assuming them to be re-tuned to make the most of the different option. I.e., comparing 1000 Ω/□ vs. 2000 Ω/□ vs. 3000 Ω/□ noting the 3k option has +-25% while the two other have just +-20% (at leas tso listed in the PDK). Regarding the lower-density MIM-cap options, I don't think they are necessarily worth it for the rather low-voltage optimized things that seem to mostly be done on wafer.space; the 1.5fF/um^2 option is rated to 10V and the 1fF/um^2 even to 20V, vs. the 2fF/um^2's 6.6V and the just 10V LD[N,P]MOS devices we have and the somehwat limiting 10~14V breakdown voltage of the Nwell/Psubstrate junction.

I wonder how we can make this clearer and where to document this?

Some "process options" details on https://wafer.space/technology.html to specify :

gf180mcuD variant
Link to the stackup page
Specify MIM option is 2fF/um^2 and High Res is 1k/sq

(edited)

Technology

Budget silicon manufacturing.

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