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Early experimentation on GF180 Tiny Tapeout GitHub action: https://github.com/urish/tt-gf180-factory-test/actions/runs/17778063270

chore: adapt for gf180mcu · urish/tt-gf180-factory-test@aca8bfd

Factory test project for Tiny Tapeout GF shuttles. Contribute to urish/tt-gf180-factory-test development by creating an account on GitHub.

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@urish - Awesome work.

Great stuff @urish

For fun I ran it on one of my old designs, and it worked: https://github.com/algofoogle/tt-gf180-toy/actions/runs/17800061560 -- I was surprised that the flow seems to define USE_POWER_PINS (and since my code was originally written to support Caravel, it's sensitive to those defines and gives a linter warning, though safe to ignore I guess).

2:14 p.m.

I was thinking about using Magic's plot to render GDS instead of the existing renderer used by the TT actions. Maybe it will look better for IHP and GF's standard cells -- I will give it a try soon.

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The verilog project template is ready! https://github.com/TinyTapeout/ttgf-verilog-template/ One caveat: the "precheck" part will fail, and that's expected. We'll fix it over the next week or two.

GitHub - TinyTapeout/ttgf-verilog-template: Submission template for...

Submission template for Tiny Tapeout GF180 (wafer.space) shuttles - Verilog HDL Projects - TinyTapeout/ttgf-verilog-template

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@urish - Should I promote that to people yet?

Everyone should be able to use the template as-is right now, but we're thinking to only open submission for people who submitted to a Tiny Tapeout shuttle in the past (our past experience shows that this is a good way to get higher quality submissions)

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@urish - BTW Have you ever tested what happens if someone shorts VDD to GND together aggressively?

5:07 a.m.

@urish - The power gating should stop it from causing any problem.

Yes, it should stop it.

5:12 a.m.

But the current shuttle won't be power gated

urish

Everyone should be able to use the template as-is right now, but we're thinking to only open submission for people who submitted to a Tiny Tapeout shuttle in the past (our past experience shows that this is a good way to get higher quality submissions)

I did one past TT, kinda have been digging around Discord looking for ideas to work on for the next run. Is there anything I can try to do with this that would be helpful?

urish started a thread. 2025-09-30 5:37 a.m.

@Tim 'mithro' Ansell The power gate stops it as long as you don't enable that particular design

If you do enable it, you will get potentially damaging high currents.

tnt

@Tim 'mithro' Ansell The power gate stops it as long as you don't enable that particular design

If you do enable it, you will get potentially damaging high currents.

But have you actually tested such a thing?

No.

6:23 a.m.

We had one design that had a short but it was through li in sky130 so it ended up drawing way more than expected and more than we recommend, but it was only ~ 15 mA which is still very much in the "chip will survive" zone.

6:25 a.m.

I had a power gate test design that was meant to test high current usage in TT07 but I made a mistake in the layout so it wasn't able to generate very high current. There is a fixed version in TT08 but given I just got the chips yesterday, I'll wait a bit before trying to burn those

We do have a way to mark dangerous projects post silicon, so users get warned before enabling them through the commander app

Will you be taking custom GDS on this run, or just digital LibreLane generated stuff?

Only LibreLane stuff. Without power gating it's a bit risky to accept random GDS

If you manually add a power gate yourself we can consider including it

7:55 a.m.

Or if might just wait for the next shuttle

Yeah makes sense, I figured that would be the case. I think I will try an assortment of digital and analog/mixed stuff in GF180 and see whichever shuttles I can get onto, whenever

BTW It's GF180MCU not GF180

-- Going to keep saying that because if successful we'll end up with multiple GF180 technologies.

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