This project implements a custom 8-bit computer inspired by the SAP (Simple-As-Possible) architecture, designed and realized entirely at the Register Transfer Level (RTL) using Verilog HDL. - navne...
Single port SRAM connected directly to TT IO pins. Contribute to FibraServiTT/TTGF26b_Arrakeen_SPSRAM_direct development by creating an account on GitHub.