wafer.space Community - This was a challenging one! After

16:17

Nice, how did you guys go about changing the default cell library ?

@Essen theoretically it should be just "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu9t5v0", in config.json BUT there is a bug in the PDK that TT is using, so @htamas had to make a patch: https://github.com/TinyTapeout/tt-gds-action/compare/main...rejunity:tt-gds-action-gf180mcu_fd_sc_mcu9t5v0:main (edited)

So basically you have to 1) clone https://github.com/TinyTapeout/tt-gds-action apply the patch 1.5) add a tag on your patched gds-action repo, I used ttgf0p2_9t 2) route your gds.yaml to use patched gds-action repo. something like that: https://github.com/rejunity/tt08-vga-drop/commit/2ac440a4bd84136deccb49f6ed56c4ded1a0a8b7 3) add "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu9t5v0", to your config.json 4) change Makefile so that Gate Level tests use correct cell library too: https://github.com/rejunity/tt08-vga-drop/commit/22135b09cfd3b970ce26098b89df31547c557192 and you should be done (edited)

18:16

You might get around 10..15% speedup from that

Nice, sounds like it was a fun ride.

(but loose in area)

Essen

Nice, sounds like it was a fun ride.

for some definition of fun...

I think we all here share a common twisted definition. (edited)

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ReJ aka Renaldas Zioma

You might get around 10..15% speedup from that

Haha, maybe I should. For now I don't have any timing issues, at least, assuming the output io doesn't go faster than 50MHz ?

I don't think this affects IO cells, only logic/dff

Yes, just to say that my timing is fine, and I am bottlenecked by the IO, so I have no motivation to up the frequency.

18:20

We need faster, open source IO so bad

18:21

Anyways, off to lunch

see you around

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Yeah, for MAC-array/SystolicArray you bound to be IO bound, I suppose

18:21

I added some "noob" input caches to my implementation, some time ago (edited)

18:22

https://github.com/rejunity/tiny-asic-1_58bit-matrix-mul

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18:23

18:25

And septenary version: https://github.com/rejunity/tt09-septenary-matrix-mul Unfortunately never got fab'd due to eFabless going bonk

ReJ aka Renaldas Zioma

And septenary version: https://github.com/rejunity/tt09-septenary-matrix-mul Unfortunately never got fab'd due to eFabless going bonk

Any plans on submitting it to a future shuttle ?

Essen

Any plans on submitting it to a future shuttle ?

Yes, for the next sky130 shuttle I would like to implementa input data cache with @tnt SRAM blocks. I am also very tempted to see how large of an array could fit onto the whole wafer.space chip... maybe even buy a wafer for that

but I don't think I will have time for the first shuttle.

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ReJ aka Renaldas Zioma

Yes, for the next sky130 shuttle I would like to implementa input data cache with @tnt SRAM blocks. I am also very tempted to see how large of an array could fit onto the whole wafer.space chip... maybe even buy a wafer for that

but I don't think I will have time for the first shuttle.

Sounds like more fun incoming

Haha, an entire wafer, I would like to see you guys do that.

ah, sorry, I didn't mean a wafer scale

though that would be fun!!! Instead wafer.space has an option to get uncut wafer for $2000 with 40 chips of your design (but someone needs to cut and package them

) but still not a bad deal because that gives approximately 128 TinyTapeout tiles worth of an area. (edited)

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Back of envelope calculation gives me around 10..20 GOPs (something like 16x20 mac array) for a whole chip on 180nm still far from 1TOps

(edited)

@EmbeddedKen this is for you :

get uncut wafer for $2000 with 40 chips of your design (but someone needs to cut and package them

)

ReJ aka Renaldas Zioma

ah, sorry, I didn't mean a wafer scale

though that would be fun!!! Instead wafer.space has an option to get uncut wafer for $2000 with 40 chips of your design (but someone needs to cut and package them

) but still not a bad deal because that gives approximately 128 TinyTapeout tiles worth of an area. (edited)

How did I miss that

Damn, looks like I also need a die bonding machine now.

20:01

How are you planning on doing the cutting and packaging ? Does one of you own the die bonding machine or know someone that does ?

Well the 2000$ option is only as an addition to the 7000$ slot.

20:03

So it's just to get a neat souvenir ... or if you want to do wafer level probing I guess.

So sad, you got my hopes up there for a second.

There is a fixed number of slots in the reticle ... so the price is pretty much production_cost / num_slots ... 2k$ is the cost to run one more wafer through the flow.

20:13

The production costs are (simplified) maskset_cost + n_wafer * wafer_processing_cost and the mask costs is the big chunks and the part which has a limited number of slots. (edited)

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Sad

1

Still a great deal though