wafer.space Community

@Greg - could you explain more about your USB stuff with Luna here?

06:58

@tnt - I have already forgotten the state of your USB core on gf180mcu

07:00

@Lofty - Have you had a chance to test your UTMI (or was it ULPI) interface yet?

Tim 'mithro' Ansell

@Lofty - Have you had a chance to test your UTMI (or was it ULPI) interface yet?

not yet (it was ULPI)

There’s https://tinytapeout.com/chips/ttgf0p2/tt_um_urish_usb_cdc on the run 1 Tiny Tapeout. I might grab that for the next TinyQV

130 USB CDC (Serial) Device - Tiny Tapeout

USB to UART bridge, 115200 baud rate

1

@urish - I think you showed that your USB-CDC design was working on the GF180MCU shuttle?

I tested it. Although it's based off the tinyfpga code, so not sure exactly how "spec compliant" it is, I never ran test suites on it to validate behavior in the various edge cases.

@Greg has been getting some stuff going @ https://github.com/gregdavill/tinyfpga-boot/actions

Workflow runs · gregdavill/tinyfpga-boot

A UF2 bootloader targeting tinyfpga bx, written in amaranth - Workflow runs · gregdavill/tinyfpga-boot

08:59

Hmmm, I should get started pre-layout-SPICE plus then drawing the MCML cells (of proportions approximately matching what the simulations suggest to be ideal) for what I had planned to get into my ttsky26a tile (an MCML partial positive feedback 2-delay-cell VCO (no inductor) plus between a mere PA to launch the clock directly and a an actual serializer launching a PRBS-31 stream to allow estimating/prediction/measuring what TX equalizer parameters would be needed). I do for now at least still have hope to squeeze a (if it had TX equalization done, at least) USB 3.0 SS (the 5Gbit/s stuff) compliant signal out of it on W.S.

09:10

I'm assuming we'd expect Run2 chips to hit testbenches at least a week before the GDS deadline for Run3?

namibj

Hmmm, I should get started pre-layout-SPICE plus then drawing the MCML cells (of proportions approximately matching what the simulations suggest to be ideal) for what I had planned to get into my ttsky26a tile (an MCML partial positive feedback 2-delay-cell VCO (no inductor) plus between a mere PA to launch the clock directly and a an actual serializer launching a PRBS-31 stream to allow estimating/prediction/measuring what TX equalizer parameters would be needed). I do for now at least still have hope to squeeze a (if it had TX equalization done, at least) USB 3.0 SS (the 5Gbit/s stuff) compliant signal out of it on W.S.

Um, did you mean to post this in #usb

Lofty

Um, did you mean to post this in #usb

He did say "hope to squeeze a USB 3.0 Super Speed compliant signal out of it on wafer.space"

namibj

I'm assuming we'd expect Run2 chips to hit testbenches at least a week before the GDS deadline for Run3?

I have yet to plan things that far ahead

Tim 'mithro' Ansell

@Greg has been getting some stuff going @ https://github.com/gregdavill/tinyfpga-boot/actions

I probably need to rename this at some point. Since with the luna backend it's supporting FS/HS(ULPI), and already builds for ECP5 and iCE40 targets. not just the tinyfpga bx.

Lofty

Um, did you mean to post this in #usb

USB 3.0 5 Gbit/s SS, PCIe 2.0, and 5GBASE-KR (which is just a 10 Gbit/s SFP+ port's PHY but for backplane (think: where PCIe would have been a normal/expected sight) which is then called 10GBASE-KR, just clocked at half with adjusted error counter thresholds/timeouts) are the 5GBaud high speed standards I hope to be feasible on gf180mcuD with at least "usable" (if not spec-compliant) link margin, to connect to modern computers. I'd expect PCIe to be the hardest to pull off (it's quite complicated), 5GBASE-KR to suffer from relatively expensive switch ports to get one's that'll do that speed (most only do 1G/10G[/25G]) but possibly lowest-overhead and lowest required buffer size (SRAM space usage!), and SS to be at most risk of sad trade-offs between SRAM allocation and feasible goodput. With luck and prayers at least TX for 10GBASE-KR should be possible though and would allow cheap exfiltration of bulk data from a W.S die. We'd know more after my SPICE trials that are looking for feasible frequency performance of the core buffer cell (needed for VCO and clock tree) and especially after that has hit layout (w/ PEX, to do post-layout SPICE of at least a VCO core and it's clock extraction/take-off clock tree buffers.

Tim 'mithro' Ansell

I have yet to plan things that far ahead

Oh I thought you at least would have an expectation and probably a "yes, per current expectations, ofc conditional on Run3 even happening".

I feel these might be possible on gf180bcd; gf180mcuD might be a stretch

namibj

Oh I thought you at least would have an expectation and probably a "yes, per current expectations, ofc conditional on Run3 even happening".

I think my goal is something like atleast 6-8 weeks between people getting back silicon and the next run closing

1

Lofty

I feel these might be possible on gf180bcd; gf180mcuD might be a stretch

Possibly! But I'm not going to stop people from trying