wafer.space Community - gf180mcu_as_sc_mcu7t3v3/example

23:48

@Tholin Sorry, but I don't think my Mac has enough umph to run a design that size. If you get partial logs/reports you can send them to me. I've seen long run times when the fill/cap cells aren't parallelized before comparison. May not be relevant.

bailey

@Tholin Sorry, but I don't think my Mac has enough umph to run a design that size. If you get partial logs/reports you can send them to me. I've seen long run times when the fill/cap cells aren't parallelized before comparison. May not be relevant.

69-netgen-lvs.zip

13.38 KB

Tholin

Click to see attachment 🖼️

Thanks, I'll check later today.

Tholin

Click to see attachment 🖼️

@Tholin the setup file for gf180mcuD provides for parallel reduction of fillcap cells but not decap cells. If you are creating a new standard cell library for gf180mcu_as_sc_mcu7t3v3 then I suggest you either, 1. rename the decap cells to fillcap to match the 5v0 libraries or 2. modify the netgen setup file to reduce parallel decap cells.

I did this and its still taking forever. There are also still warnings in the log that I don”t see with the 5V SCL

17:27

Tholin

I did this and its still taking forever. There are also still warnings in the log that I don”t see with the 5V SCL

The first is due to yosys adding buffers to increase capacitance on nets (I think). The outputs are unconnected - normal. The second is netgen output saying that it was told to ignore a parameter that did not exist on a device - also normal. If you could send me the partial log, I can take a look at it.