wafer.space Community - I am very new to LibreLane so I'm not

10:55

Hi! You need to look in 06-yosys-synthesis for the Yosys log. The checks are running in a later step.

06-yosys-synthesis/yosys-synthesis.log

1

10:56

if it begins with "yosys" it's a yosys pass, if it begins with "checker" it's not a yosys pass

OHHH alt thx I'll look into it!!

(Leo's a LibreLane maintainer, and I'm a Yosys dev, so we'd both be happy to help with issues you might have)

Oh that's so awesome! Very glad to have you helping! <3

11:03

I'll let you both know what the issues were and if I managed to fix them or need a hand with em lol

This is the log. It seems to complain about the bidir configuration???

68.29 KB

11:59

Any clues on waht the fix might be? It says multiple conflicting drivers :(

According to this it's becaue I'm using the register in multiple places? huuuuh

Dory

According to this it's becaue I'm using the register in multiple places? huuuuh

no, it's not that you're using it in multiple places, it's that you're driving it in multiple places

fair

librelane should lint your code with Verilator - 01-verilator-lint; what does it have to say

Turned up being that I was doing:

...
s0 <= bidir_in;
s1 <= bidir_in;
...

that shouldn't cause issues.

Upon removing it the issue stopped showing up

14:45

Rn I'm just testing my workflow but if this comes back to bite my ass I will lyk

14:45

-# I just want to make sure I can generate the silicon and goddamit is it not wanting to

@Lofty mind if I share my code with you? I updated it and it is back to causing "multiple driver" issues xd

Dory

@Lofty mind if I share my code with you? I updated it and it is back to causing "multiple driver" issues xd

Sure.