@Leo Moser (mole99) - Forgive me if these things are stupid / don't make sense but I had some random thoughts / ideas about ways we should probably modify the "default" template / setup for the padring / pads based on random theories from being at the bond house.
Firstly, the pads seem like they are currently very close to the edge of the die. Looking through the microscope they kinda look like they almost connected to it. I assume they must not be, otherwise nothing would work but it was concerning the first time I looked at them.
Could we add a bit more space between the pads and the edge/seal ring?
I know it reduces the available silicon area but I /think/ it should help have more margin there.
Changing padring would mean we have an issue for TT because changing silicon area means we might need to change the size of tiles (and worst case, even size of power gates meaning we'd need to re-design them ... meaning closing the shuttle)
06:42
The passivation already looks like that drawing. The metal pad is 65.35 um x 68 um and tha passivation opening is 60 x 60 um.
06:46
Distance from guard ring to pads meets GR.2 ( It's 10 um from the marking layer and 11 um away from the actual pad ). That's more than twice the clearance between pad and first power ring.
But I also might be suggesting things which make no sense
06:58
@tnt - If I understand correctly, Tiny Tapeout/you are doing your own bonding (even if we are at the same place) - so that is not something that effects you?
Well one thing we were thinking about is to also offer the TT chips on the standard WS breakout for if people want to use in their own PCB. ( So you'd get the standard TT demo+breakout and also TT chips on the WS breakout ).
07:01
I think the repo above doesn't have seal ring and fill, this was added later by GF ? Not sure if they sent back the altered gds ...
07:01
( I can't check ... can't figure out how to actually download the files from the repo above .. )
07:02
But let's see how it works out with the next set of wafers ...
07:02
When do you think you'll start trying with those ?
tnt
Well one thing we were thinking about is to also offer the TT chips on the standard WS breakout for if people want to use in their own PCB. ( So you'd get the standard TT demo+breakout and also TT chips on the WS breakout ).
That would be cool!
I'm just throwing stuff out there. It might make sense to do some type of tests along these lines to see if they make any difference.
tnt
I think the repo above doesn't have seal ring and fill, this was added later by GF ? Not sure if they sent back the altered gds ...
I'm guessing someone like @azonenberg or @BreakingTaps will eventually look into. I will try and make sure they have some samples.
I'm also trying to figure out if there are any failure analysis labs with SEMs in the Shenzhen area that are within my price range that we can get stuff done with too.
parallel lapping and cross-sectioning my chip are on the eventual-todo list (time permitting, have to do it after-hours at work)
What failure in particular would I be looking out for?(edited)
It's not the same bond no. But strangely they seem grouped on the same side of the chip ... it's not the same side on every chip but on a given chip I'll have 1 side perfect and another with all the failed bonds.
14:58
( I'm only testing 2 sides because the samples I got have "survivor bias", they were the one passing the digital test which tests North/South side at the factory ... but the East/West were not tested at the factory ).
If @BreakingTaps has a multimeter, it's pretty easy to test .. Use diode more, put positive lead on GND on one of the cap, then probe along the connector for the IOs. Good ones should show roughly 0.75V.
).
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